1. Field of the Invention
The invention relates to a high density semiconductor package, and more particularly to a thin high-density semiconductor package.
2. Description of the Related Art
Semiconductor package is essential for connecting chips with an external circuit board such as a printed circuit board (PCB). To connect a chip and a package substrate, wires or bumps are usually used as connection media. Flip Chip Interconnection Technology is utilized to form bumps in an array on bonding pads of a chip and after the chip being flipped, the chip can be electrically connected to the package substrate. The chip is electrically connected with external signal terminals through the internal circuits and connection pads of the substrate. The structure of packages has become increasingly versatile with increasing package density of chips. The chip package using the Flip Chip Interconnection Technology described above has several advantages including reductions in package area and signal transmission pathways. Therefore, the Flip Chip Interconnection Technology has been widely used in the industry of chip package. A Multi-Chip Module, for example, is a package structure in which several package modules of Chip Scale Package (CSP) are mounted on a single substrate by using the Flip Chip Interconnection Technology. The package modules are electrically connected with each other through the substrate.
Several dynamic random access memories (DRAMs) and one Central Process Unit (CPU), for example, can be packaged on a single substrate in a MCM type, which is capable of increasing package density, save space, as well as reduce the signal delay between the package modules. Consequently, high-speed data processing can be achieved by the MCM package, which is widely used in communication and portable electronic products.
FIGS. 1A and 1B are schematic cross-sectional and top views of a conventional package structure with multiple package modules disposed on a motherboard 10. Referring to FIGS. 1A and 1B, the package structure includes a substrate 100, a first package module 110, and four second package modules 112. The two surfaces 102 and 104 of the substrate 100 are respectively provided with a plurality of connection pads (not shown) as input/output media for the internal circuits in the substrate 100. The first package module 110, for example, comprised of a CPU, is provided in the central area of the lower surface 102 of the substrate 100, and the second package modules 112, for example, comprised of four DRAMs, are located on the four corners of the upper surface 104 of the substrate 100. In addition, the first package module 110 and the second package modules 112 are electrically connected with the substrate 100 by using the bumps 106. An underfill 108 is dispensed between the package modules 110, 112 and the substrate 100 and surrounding the bumps 106 to buffer stress resulting from the different coefficients of thermal expansion between the package modules 110, 112 and the substrate 100. For example, if the stress occurs, cracks can be generated in the bumps 106, and thereby adversely affecting the quality of the signal transmissions between the package modules 110, 112 and the substrate 100.
Further, as shown in FIGS. 1A and 1B, the total thickness D of the package structure is the sum of the thickness of the substrate 100, the first package module 110 and the second package module 112, which is relatively large, and therefore do not conform to the trend of lightness, thinness, shortness, and smallness. Moreover, when the chip inside the first package module 110 is operated in high frequency, a large amount of heat will be generated, leading to a drastic increase in the temperature of the chip. It is noted that, once the temperature rises above the normal operating temperature range, the internal circuits of the chip will behave erroneously or malfunction temporarily. Moreover, the first package module 110, a CPU, for example, is disposed on the lower surface 102 of the substrate 100, making it impossible to install heat sink member on the CPU. Even if the heat of the CPU can be dissipated through the motherboard 10, it cannot be dissipated effectively.